library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity link_controller8_tb is
end link_controller8_tb; 

architecture tb of link_controller8_tb is
  
  --------------------------------------------------------------------------------------------------------
  --
  -- components 
  --
  -- components used are defined here
  --
  --------------------------------------------------------------------------------------------------------
  component link_controller is

    port ( clk          		: in  std_logic;
           host_address 		: in  std_logic_vector(31 DownTo 0);
           pixel_value      : in  std_logic;
           data_in_n    		: in  std_logic;
           data_in_ne   		: in  std_logic;
           data_in_nw   		: in  std_logic;
           data_in_s    		: in  std_logic;
           data_in_se   		: in  std_logic;
           data_in_sw   		: in  std_logic;
           data_in_e    		: in  std_logic;
           data_in_w    		: in  std_logic;
           data_out_n   		: out std_logic;
           data_out_ne  		: out std_logic;
           data_out_nw  		: out std_logic;
           data_out_s   		: out std_logic;
           data_out_se  		: out std_logic;
           data_out_sw  		: out std_logic;
           data_out_e   		: out std_logic;
           data_out_w   		: out std_logic;
           links_complete   : out std_logic;
           controller_label : out std_logic_vector(31 DownTo 0)
         );
   
  end component;

  component link_physical is

    port ( link_a   : in  std_logic;
           link_b   : in  std_logic;
           or_out   : out std_logic
         );

  end component;

  --------------------------------------------------------------------------------------------------------
  --
  -- global signals
  --
  -- all global signals used across controllers are defined here
  --
  --------------------------------------------------------------------------------------------------------
  signal controller_clk 											: std_logic;

  --------------------------------------------------------------------------------------------------------
  --
  -- link signals
  --
  -- physical link signals for active controllers
  --
  --------------------------------------------------------------------------------------------------------

  signal physical_link_1_2              			: std_logic;
  signal physical_link_1_3              			: std_logic;
  signal physical_link_1_4              			: std_logic;
  signal physical_link_2_3              			: std_logic;
  signal physical_link_2_4              			: std_logic;
  signal physical_link_3_4              			: std_logic;

  --------------------------------------------------------------------------------------------------------
  --
  -- boundary link signals
  --
  -- physical link signals between active controllers and boundary controllers
  --
  --------------------------------------------------------------------------------------------------------

  signal physical_link_1_90             			: std_logic;
  signal physical_link_1_91             			: std_logic;
  signal physical_link_1_92             			: std_logic;
  signal physical_link_1_94             			: std_logic;
  signal physical_link_1_96             			: std_logic;

  signal physical_link_2_91             			: std_logic;
  signal physical_link_2_92             			: std_logic;
  signal physical_link_2_93             			: std_logic;
  signal physical_link_2_95             			: std_logic;
  signal physical_link_2_97             			: std_logic;

  signal physical_link_3_94             			: std_logic;
  signal physical_link_3_96             			: std_logic;
  signal physical_link_3_98             			: std_logic;
  signal physical_link_3_99             			: std_logic;
  signal physical_link_3_100            			: std_logic;

  signal physical_link_4_99             			: std_logic;
  signal physical_link_4_100            			: std_logic;
  signal physical_link_4_101            			: std_logic;
  signal physical_link_4_97             			: std_logic;
  signal physical_link_4_95             			: std_logic;

  --------------------------------------------------------------------------------------------------------
  --
  -- loop back link signals
  --
  -- loop back link signals for boundary controllers
  --
  --------------------------------------------------------------------------------------------------------

  signal p_l_loop_90_n         			: std_logic;
  signal p_l_loop_90_ne        			: std_logic;
  signal p_l_loop_90_nw        			: std_logic;
  signal p_l_loop_90_s         			: std_logic;
  signal p_l_loop_90_sw        			: std_logic;
  signal p_l_loop_90_e         			: std_logic;
  signal p_l_loop_90_w         			: std_logic;

  signal p_l_loop_91_n         			: std_logic;
  signal p_l_loop_91_ne        			: std_logic;
  signal p_l_loop_91_nw        			: std_logic;
  signal p_l_loop_91_sw        			: std_logic;
  signal p_l_loop_91_e         			: std_logic;
  signal p_l_loop_91_w         			: std_logic;

  signal p_l_loop_92_n         			: std_logic;
  signal p_l_loop_92_ne        			: std_logic;
  signal p_l_loop_92_nw        			: std_logic;
  signal p_l_loop_92_se        			: std_logic;
  signal p_l_loop_92_e         			: std_logic;
  signal p_l_loop_92_w         			: std_logic;

  signal p_l_loop_93_n         			: std_logic;
  signal p_l_loop_93_ne        			: std_logic;
  signal p_l_loop_93_nw        			: std_logic;
  signal p_l_loop_93_s         			: std_logic;
  signal p_l_loop_93_se        			: std_logic;
  signal p_l_loop_93_e         			: std_logic;
  signal p_l_loop_93_w         			: std_logic;

  signal p_l_loop_94_n         			: std_logic;
  signal p_l_loop_94_ne        			: std_logic;
  signal p_l_loop_94_nw        			: std_logic;
  signal p_l_loop_94_s         			: std_logic;
  signal p_l_loop_94_sw        			: std_logic;
  signal p_l_loop_94_w         			: std_logic;

  signal p_l_loop_95_n         			: std_logic;
  signal p_l_loop_95_ne        			: std_logic;
  signal p_l_loop_95_nw        			: std_logic;
  signal p_l_loop_95_s         			: std_logic;
  signal p_l_loop_95_se        			: std_logic;
  signal p_l_loop_95_sw        			: std_logic;
  signal p_l_loop_95_e         			: std_logic;

  signal p_l_loop_96_n         			: std_logic;
  signal p_l_loop_96_nw        			: std_logic;
  signal p_l_loop_96_s         			: std_logic;
  signal p_l_loop_96_se        			: std_logic;
  signal p_l_loop_96_sw        			: std_logic;
  signal p_l_loop_96_w         			: std_logic;

  signal p_l_loop_97_n         			: std_logic;
  signal p_l_loop_97_ne        			: std_logic;
  signal p_l_loop_97_s         			: std_logic;
  signal p_l_loop_97_se        			: std_logic;
  signal p_l_loop_97_sw        			: std_logic;
  signal p_l_loop_97_e         			: std_logic;

  signal p_l_loop_98_n         			: std_logic;
  signal p_l_loop_98_ne        			: std_logic;
  signal p_l_loop_98_nw        			: std_logic;
  signal p_l_loop_98_s         			: std_logic;
  signal p_l_loop_98_se        			: std_logic;
  signal p_l_loop_98_sw        			: std_logic;
  signal p_l_loop_98_e         			: std_logic;
  signal p_l_loop_98_w         			: std_logic;

  signal p_l_loop_99_ne        			: std_logic;
  signal p_l_loop_99_nw        			: std_logic;
  signal p_l_loop_99_s         			: std_logic;
  signal p_l_loop_99_se        			: std_logic;
  signal p_l_loop_99_sw        			: std_logic;
  signal p_l_loop_99_e         			: std_logic;
  signal p_l_loop_99_w         			: std_logic;

  signal p_l_loop_100_ne        		: std_logic;
  signal p_l_loop_100_nw        		: std_logic;
  signal p_l_loop_100_s         		: std_logic;
  signal p_l_loop_100_se        		: std_logic;
  signal p_l_loop_100_sw        		: std_logic;
  signal p_l_loop_100_e         		: std_logic;
  signal p_l_loop_100_w         		: std_logic;

  signal p_l_loop_101_n         		: std_logic;
  signal p_l_loop_101_nw        		: std_logic;
  signal p_l_loop_101_s         		: std_logic;
  signal p_l_loop_101_se        		: std_logic;
  signal p_l_loop_101_sw        		: std_logic;
  signal p_l_loop_101_e         		: std_logic;
  signal p_l_loop_101_w         		: std_logic;

  --------------------------------------------------------------------------------------------------------
  --
  -- controller signals
  --
  -- all controller signals are defined here
  --
  --------------------------------------------------------------------------------------------------------

  -- link 1 signals
  signal link_1_address  								      : std_logic_vector(31 DownTo 0);
  signal link_1_controller_pixel    			    : std_logic;
  signal link_1_controller_complete 			    : std_logic;
  signal link_1_controller_final_label        : std_logic_vector(31 DownTo 0);
  signal link_1_out_n                         : std_logic;
  signal link_1_out_ne                        : std_logic;
  signal link_1_out_nw                        : std_logic;
  signal link_1_out_s                         : std_logic;
  signal link_1_out_se                        : std_logic;
  signal link_1_out_sw                        : std_logic;
  signal link_1_out_e                         : std_logic;
  signal link_1_out_w                         : std_logic;

  -- link 2 signals
  signal link_2_address  								      : std_logic_vector(31 DownTo 0);
  signal link_2_controller_pixel    			    : std_logic;
  signal link_2_controller_complete 			    : std_logic;
  signal link_2_controller_final_label        : std_logic_vector(31 DownTo 0);
  signal link_2_out_n                         : std_logic;
  signal link_2_out_ne                        : std_logic;
  signal link_2_out_nw                        : std_logic;
  signal link_2_out_s                         : std_logic;
  signal link_2_out_se                        : std_logic;
  signal link_2_out_sw                        : std_logic;
  signal link_2_out_e                         : std_logic;
  signal link_2_out_w                         : std_logic;

  -- link 3 signals
  signal link_3_address  								      : std_logic_vector(31 DownTo 0);
  signal link_3_controller_pixel    			    : std_logic;
  signal link_3_controller_complete 			    : std_logic;
  signal link_3_controller_final_label        : std_logic_vector(31 DownTo 0);
  signal link_3_out_n                         : std_logic;
  signal link_3_out_ne                        : std_logic;
  signal link_3_out_nw                        : std_logic;
  signal link_3_out_s                         : std_logic;
  signal link_3_out_se                        : std_logic;
  signal link_3_out_sw                        : std_logic;
  signal link_3_out_e                         : std_logic;
  signal link_3_out_w                         : std_logic;

  -- link 4 signals
  signal link_4_address  								      : std_logic_vector(31 DownTo 0);
  signal link_4_controller_pixel    			    : std_logic;
  signal link_4_controller_complete 			    : std_logic;
  signal link_4_controller_final_label        : std_logic_vector(31 DownTo 0);
  signal link_4_out_n                         : std_logic;
  signal link_4_out_ne                        : std_logic;
  signal link_4_out_nw                        : std_logic;
  signal link_4_out_s                         : std_logic;
  signal link_4_out_se                        : std_logic;
  signal link_4_out_sw                        : std_logic;
  signal link_4_out_e                         : std_logic;
  signal link_4_out_w                         : std_logic;

  -- link 90 signals
  signal link_90_address  								    : std_logic_vector(31 DownTo 0);
  signal link_90_controller_pixel    			    : std_logic;
  signal link_90_controller_complete 			    : std_logic;
  signal link_90_controller_final_label       : std_logic_vector(31 DownTo 0);
  signal link_90_out_n                        : std_logic;
  signal link_90_out_ne                       : std_logic;
  signal link_90_out_nw                       : std_logic;
  signal link_90_out_s                        : std_logic;
  signal link_90_out_se                       : std_logic;
  signal link_90_out_sw                       : std_logic;
  signal link_90_out_e                        : std_logic;
  signal link_90_out_w                        : std_logic;

  -- link 91 signals
  signal link_91_address  								    : std_logic_vector(31 DownTo 0);
  signal link_91_controller_pixel    			    : std_logic;
  signal link_91_controller_complete 			    : std_logic;
  signal link_91_controller_final_label       : std_logic_vector(31 DownTo 0);
  signal link_91_out_n                        : std_logic;
  signal link_91_out_ne                       : std_logic;
  signal link_91_out_nw                       : std_logic;
  signal link_91_out_s                        : std_logic;
  signal link_91_out_se                       : std_logic;
  signal link_91_out_sw                       : std_logic;
  signal link_91_out_e                        : std_logic;
  signal link_91_out_w                        : std_logic;

  -- link 92 signals
  signal link_92_address  								    : std_logic_vector(31 DownTo 0);
  signal link_92_controller_pixel    			    : std_logic;
  signal link_92_controller_complete 			    : std_logic;
  signal link_92_controller_final_label       : std_logic_vector(31 DownTo 0);
  signal link_92_out_n                        : std_logic;
  signal link_92_out_ne                       : std_logic;
  signal link_92_out_nw                       : std_logic;
  signal link_92_out_s                        : std_logic;
  signal link_92_out_se                       : std_logic;
  signal link_92_out_sw                       : std_logic;
  signal link_92_out_e                        : std_logic;
  signal link_92_out_w                        : std_logic;

  -- link 93 signals
  signal link_93_address  								    : std_logic_vector(31 DownTo 0);
  signal link_93_controller_pixel    			    : std_logic;
  signal link_93_controller_complete 			    : std_logic;
  signal link_93_controller_final_label       : std_logic_vector(31 DownTo 0);
  signal link_93_out_n                        : std_logic;
  signal link_93_out_ne                       : std_logic;
  signal link_93_out_nw                       : std_logic;
  signal link_93_out_s                        : std_logic;
  signal link_93_out_se                       : std_logic;
  signal link_93_out_sw                       : std_logic;
  signal link_93_out_e                        : std_logic;
  signal link_93_out_w                        : std_logic;

  -- link 94 signals
  signal link_94_address  								    : std_logic_vector(31 DownTo 0);
  signal link_94_controller_pixel    			    : std_logic;
  signal link_94_controller_complete 			    : std_logic;
  signal link_94_controller_final_label       : std_logic_vector(31 DownTo 0);
  signal link_94_out_n                        : std_logic;
  signal link_94_out_ne                       : std_logic;
  signal link_94_out_nw                       : std_logic;
  signal link_94_out_s                        : std_logic;
  signal link_94_out_se                       : std_logic;
  signal link_94_out_sw                       : std_logic;
  signal link_94_out_e                        : std_logic;
  signal link_94_out_w                        : std_logic;

  -- link 95 signals
  signal link_95_address  								    : std_logic_vector(31 DownTo 0);
  signal link_95_controller_pixel    			    : std_logic;
  signal link_95_controller_complete 			    : std_logic;
  signal link_95_controller_final_label       : std_logic_vector(31 DownTo 0);
  signal link_95_out_n                        : std_logic;
  signal link_95_out_ne                       : std_logic;
  signal link_95_out_nw                       : std_logic;
  signal link_95_out_s                        : std_logic;
  signal link_95_out_se                       : std_logic;
  signal link_95_out_sw                       : std_logic;
  signal link_95_out_e                        : std_logic;
  signal link_95_out_w                        : std_logic;

  -- link 96 signals
  signal link_96_address  								    : std_logic_vector(31 DownTo 0);
  signal link_96_controller_pixel    			    : std_logic;
  signal link_96_controller_complete 			    : std_logic;
  signal link_96_controller_final_label       : std_logic_vector(31 DownTo 0);
  signal link_96_out_n                        : std_logic;
  signal link_96_out_ne                       : std_logic;
  signal link_96_out_nw                       : std_logic;
  signal link_96_out_s                        : std_logic;
  signal link_96_out_se                       : std_logic;
  signal link_96_out_sw                       : std_logic;
  signal link_96_out_e                        : std_logic;
  signal link_96_out_w                        : std_logic;

  -- link 97 signals
  signal link_97_address  								    : std_logic_vector(31 DownTo 0);
  signal link_97_controller_pixel    			    : std_logic;
  signal link_97_controller_complete 			    : std_logic;
  signal link_97_controller_final_label       : std_logic_vector(31 DownTo 0);
  signal link_97_out_n                        : std_logic;
  signal link_97_out_ne                       : std_logic;
  signal link_97_out_nw                       : std_logic;
  signal link_97_out_s                        : std_logic;
  signal link_97_out_se                       : std_logic;
  signal link_97_out_sw                       : std_logic;
  signal link_97_out_e                        : std_logic;
  signal link_97_out_w                        : std_logic;

  -- link 98 signals
  signal link_98_address  								    : std_logic_vector(31 DownTo 0);
  signal link_98_controller_pixel    			    : std_logic;
  signal link_98_controller_complete 			    : std_logic;
  signal link_98_controller_final_label       : std_logic_vector(31 DownTo 0);
  signal link_98_out_n                        : std_logic;
  signal link_98_out_ne                       : std_logic;
  signal link_98_out_nw                       : std_logic;
  signal link_98_out_s                        : std_logic;
  signal link_98_out_se                       : std_logic;
  signal link_98_out_sw                       : std_logic;
  signal link_98_out_e                        : std_logic;
  signal link_98_out_w                        : std_logic;

  -- link 99 signals
  signal link_99_address  								    : std_logic_vector(31 DownTo 0);
  signal link_99_controller_pixel    			    : std_logic;
  signal link_99_controller_complete 			    : std_logic;
  signal link_99_controller_final_label       : std_logic_vector(31 DownTo 0);
  signal link_99_out_n                        : std_logic;
  signal link_99_out_ne                       : std_logic;
  signal link_99_out_nw                       : std_logic;
  signal link_99_out_s                        : std_logic;
  signal link_99_out_se                       : std_logic;
  signal link_99_out_sw                       : std_logic;
  signal link_99_out_e                        : std_logic;
  signal link_99_out_w                        : std_logic;

  -- link 100 signals
  signal link_100_address  								    : std_logic_vector(31 DownTo 0);
  signal link_100_controller_pixel    			  : std_logic;
  signal link_100_controller_complete 			  : std_logic;
  signal link_100_controller_final_label      : std_logic_vector(31 DownTo 0);
  signal link_100_out_n                       : std_logic;
  signal link_100_out_ne                      : std_logic;
  signal link_100_out_nw                      : std_logic;
  signal link_100_out_s                       : std_logic;
  signal link_100_out_se                      : std_logic;
  signal link_100_out_sw                      : std_logic;
  signal link_100_out_e                       : std_logic;
  signal link_100_out_w                       : std_logic;

  -- link 101 signals
  signal link_101_address  								    : std_logic_vector(31 DownTo 0);
  signal link_101_controller_pixel    			  : std_logic;
  signal link_101_controller_complete 			  : std_logic;
  signal link_101_controller_final_label      : std_logic_vector(31 DownTo 0);
  signal link_101_out_n                       : std_logic;
  signal link_101_out_ne                      : std_logic;
  signal link_101_out_nw                      : std_logic;
  signal link_101_out_s                       : std_logic;
  signal link_101_out_se                      : std_logic;
  signal link_101_out_sw                      : std_logic;
  signal link_101_out_e                       : std_logic;
  signal link_101_out_w                       : std_logic;


begin

  --------------------------------------------------------------------------------------------------------
  --
  -- controllers
  --
  -- all controllers are set up here
  --
  --------------------------------------------------------------------------------------------------------

  link_controller_1     : link_controller port map ( controller_clk,
                                                     link_1_address,
                                                     link_1_controller_pixel,
                                                     physical_link_1_91,
                                                     physical_link_1_92,
                                                     physical_link_1_90,
                                                     physical_link_1_3,
                                                     physical_link_1_4,
                                                     physical_link_1_96,
                                                     physical_link_1_2,
                                                     physical_link_1_94,
                                                     link_1_out_n,
                                                     link_1_out_ne,
                                                     link_1_out_nw,
                                                     link_1_out_s,
                                                     link_1_out_se,
                                                     link_1_out_sw,
                                                     link_1_out_e,
                                                     link_1_out_w,
                                                     link_1_controller_complete,
                                                     link_1_controller_final_label
                                                   );

  link_controller_2     : link_controller port map ( controller_clk,
                                                     link_2_address,
                                                     link_2_controller_pixel,
                                                     physical_link_2_92,
                                                     physical_link_2_93,
                                                     physical_link_2_91,
                                                     physical_link_2_4,
                                                     physical_link_2_97,
                                                     physical_link_2_3,
                                                     physical_link_2_95,
                                                     physical_link_1_2,
                                                     link_2_out_n,
                                                     link_2_out_ne,
                                                     link_2_out_nw,
                                                     link_2_out_s,
                                                     link_2_out_se,
                                                     link_2_out_sw,
                                                     link_2_out_e,
                                                     link_2_out_w,
                                                     link_2_controller_complete,
                                                     link_2_controller_final_label
                                                   );

  link_controller_3     : link_controller port map ( controller_clk,
                                                     link_3_address,
                                                     link_3_controller_pixel,
                                                     physical_link_1_3,
                                                     physical_link_2_3,
                                                     physical_link_3_94,
                                                     physical_link_3_99,
                                                     physical_link_3_100,
                                                     physical_link_3_98,
                                                     physical_link_3_4,
                                                     physical_link_3_96,
                                                     link_3_out_n,
                                                     link_3_out_ne,
                                                     link_3_out_nw,
                                                     link_3_out_s,
                                                     link_3_out_se,
                                                     link_3_out_sw,
                                                     link_3_out_e,
                                                     link_3_out_w,
                                                     link_3_controller_complete,
                                                     link_3_controller_final_label
                                                   );

  link_controller_4     : link_controller port map ( controller_clk,
                                                     link_4_address,
                                                     link_4_controller_pixel,
                                                     physical_link_2_4,
                                                     physical_link_4_95,
                                                     physical_link_1_4,
                                                     physical_link_4_100,
                                                     physical_link_4_101,
                                                     physical_link_4_99,
                                                     physical_link_4_97,
                                                     physical_link_3_4,
                                                     link_4_out_n,
                                                     link_4_out_ne,
                                                     link_4_out_nw,
                                                     link_4_out_s,
                                                     link_4_out_se,
                                                     link_4_out_sw,
                                                     link_4_out_e,
                                                     link_4_out_w,
                                                     link_4_controller_complete,
                                                     link_4_controller_final_label
                                                   );

  link_controller_90    : link_controller port map ( controller_clk,
                                                     link_90_address,
                                                     link_90_controller_pixel,
                                                     p_l_loop_90_n,
                                                     p_l_loop_90_ne,
                                                     p_l_loop_90_nw,
                                                     p_l_loop_90_s,
                                                     physical_link_1_90,
                                                     p_l_loop_90_sw,
                                                     p_l_loop_90_e,
                                                     p_l_loop_90_w,
                                                     link_90_out_n,
                                                     link_90_out_ne,
                                                     link_90_out_nw,
                                                     link_90_out_s,
                                                     link_90_out_se,
                                                     link_90_out_sw,
                                                     link_90_out_e,
                                                     link_90_out_w,
                                                     link_90_controller_complete,
                                                     link_90_controller_final_label
                                                   );

  link_controller_91    : link_controller port map ( controller_clk,
                                                     link_91_address,
                                                     link_91_controller_pixel,
                                                     p_l_loop_91_n,
                                                     p_l_loop_91_ne,
                                                     p_l_loop_91_nw,
                                                     physical_link_1_91,
                                                     physical_link_2_91,
                                                     p_l_loop_91_sw,
                                                     p_l_loop_91_e,
                                                     p_l_loop_91_w,
                                                     link_91_out_n,
                                                     link_91_out_ne,
                                                     link_91_out_nw,
                                                     link_91_out_s,
                                                     link_91_out_se,
                                                     link_91_out_sw,
                                                     link_91_out_e,
                                                     link_91_out_w,
                                                     link_91_controller_complete,
                                                     link_91_controller_final_label
                                                   );

  link_controller_92    : link_controller port map ( controller_clk,
                                                     link_92_address,
                                                     link_92_controller_pixel,
                                                     p_l_loop_92_n,
                                                     p_l_loop_92_ne,
                                                     p_l_loop_92_nw,
                                                     physical_link_2_92,
                                                     p_l_loop_92_se,
                                                     physical_link_1_92,
                                                     p_l_loop_92_e,
                                                     p_l_loop_92_w,
                                                     link_92_out_n,
                                                     link_92_out_ne,
                                                     link_92_out_nw,
                                                     link_92_out_s,
                                                     link_92_out_se,
                                                     link_92_out_sw,
                                                     link_92_out_e,
                                                     link_92_out_w,
                                                     link_92_controller_complete,
                                                     link_92_controller_final_label
                                                   );

  link_controller_93    : link_controller port map ( controller_clk,
                                                     link_93_address,
                                                     link_93_controller_pixel,
                                                     p_l_loop_93_n,
                                                     p_l_loop_93_ne,
                                                     p_l_loop_93_nw,
                                                     p_l_loop_93_s,
                                                     p_l_loop_93_se,
                                                     physical_link_2_93,
                                                     p_l_loop_93_e,
                                                     p_l_loop_93_w,
                                                     link_93_out_n,
                                                     link_93_out_ne,
                                                     link_93_out_nw,
                                                     link_93_out_s,
                                                     link_93_out_se,
                                                     link_93_out_sw,
                                                     link_93_out_e,
                                                     link_93_out_w,
                                                     link_93_controller_complete,
                                                     link_93_controller_final_label
                                                   );

  link_controller_94    : link_controller port map ( controller_clk,
                                                     link_94_address,
                                                     link_94_controller_pixel,
                                                     p_l_loop_94_n,
                                                     p_l_loop_94_ne,
                                                     p_l_loop_94_nw,
                                                     p_l_loop_94_s,
                                                     physical_link_3_94,
                                                     p_l_loop_94_sw,
                                                     physical_link_1_94,
                                                     p_l_loop_94_w,
                                                     link_94_out_n,
                                                     link_94_out_ne,
                                                     link_94_out_nw,
                                                     link_94_out_s,
                                                     link_94_out_se,
                                                     link_94_out_sw,
                                                     link_94_out_e,
                                                     link_94_out_w,
                                                     link_94_controller_complete,
                                                     link_94_controller_final_label
                                                   );

  link_controller_95    : link_controller port map ( controller_clk,
                                                     link_95_address,
                                                     link_95_controller_pixel,
                                                     p_l_loop_95_n,
                                                     p_l_loop_95_ne,
                                                     p_l_loop_95_nw,
                                                     p_l_loop_95_s,
                                                     p_l_loop_95_se,
                                                     physical_link_4_95,
                                                     p_l_loop_95_e,
                                                     physical_link_2_95,
                                                     link_95_out_n,
                                                     link_95_out_ne,
                                                     link_95_out_nw,
                                                     link_95_out_s,
                                                     link_95_out_se,
                                                     link_95_out_sw,
                                                     link_95_out_e,
                                                     link_95_out_w,
                                                     link_95_controller_complete,
                                                     link_95_controller_final_label
                                                   );

  link_controller_96    : link_controller port map ( controller_clk,
                                                     link_96_address,
                                                     link_96_controller_pixel,
                                                     p_l_loop_96_n,
                                                     physical_link_1_96,
                                                     p_l_loop_96_nw,
                                                     p_l_loop_96_s,
                                                     p_l_loop_96_se,
                                                     p_l_loop_96_sw,
                                                     physical_link_3_96,
                                                     p_l_loop_96_w,
                                                     link_96_out_n,
                                                     link_96_out_ne,
                                                     link_96_out_nw,
                                                     link_96_out_s,
                                                     link_96_out_se,
                                                     link_96_out_sw,
                                                     link_96_out_e,
                                                     link_96_out_w,
                                                     link_96_controller_complete,
                                                     link_96_controller_final_label
                                                   );

  link_controller_97    : link_controller port map ( controller_clk,
                                                     link_97_address,
                                                     link_97_controller_pixel,
                                                     p_l_loop_97_n,
                                                     p_l_loop_97_ne,
                                                     physical_link_2_97,
                                                     p_l_loop_97_s,
                                                     p_l_loop_97_se,
                                                     p_l_loop_97_sw,
                                                     p_l_loop_97_e,
                                                     physical_link_4_97,
                                                     link_97_out_n,
                                                     link_97_out_ne,
                                                     link_97_out_nw,
                                                     link_97_out_s,
                                                     link_97_out_se,
                                                     link_97_out_sw,
                                                     link_97_out_e,
                                                     link_97_out_w,
                                                     link_97_controller_complete,
                                                     link_97_controller_final_label
                                                   );

  link_controller_98    : link_controller port map ( controller_clk,
                                                     link_98_address,
                                                     link_98_controller_pixel,
                                                     p_l_loop_98_n,
                                                     p_l_loop_98_ne,
                                                     p_l_loop_98_nw,
                                                     p_l_loop_98_s,
                                                     p_l_loop_98_se,
                                                     p_l_loop_98_sw,
                                                     p_l_loop_98_e,
                                                     p_l_loop_98_w,
                                                     link_98_out_n,
                                                     link_98_out_ne,
                                                     link_98_out_nw,
                                                     link_98_out_s,
                                                     link_98_out_se,
                                                     link_98_out_sw,
                                                     link_98_out_e,
                                                     link_98_out_w,
                                                     link_98_controller_complete,
                                                     link_98_controller_final_label
                                                   );

  link_controller_99    : link_controller port map ( controller_clk,
                                                     link_99_address,
                                                     link_99_controller_pixel,
                                                     physical_link_3_99,
                                                     p_l_loop_99_ne,
                                                     physical_link_4_99,
                                                     p_l_loop_99_s, 
                                                     p_l_loop_99_se,
                                                     p_l_loop_99_sw,
                                                     p_l_loop_99_e,
                                                     p_l_loop_99_w,
                                                     link_99_out_n,
                                                     link_99_out_ne,
                                                     link_99_out_nw,
                                                     link_99_out_s,
                                                     link_99_out_se,
                                                     link_99_out_sw,
                                                     link_99_out_e,
                                                     link_99_out_w,
                                                     link_99_controller_complete,
                                                     link_99_controller_final_label
                                                   );

  link_controller_100   : link_controller port map ( controller_clk,
                                                     link_100_address,
                                                     link_100_controller_pixel,
                                                     physical_link_4_100,
                                                     physical_link_3_100,
                                                     p_l_loop_100_nw,
                                                     p_l_loop_100_s,
                                                     p_l_loop_100_se,
                                                     p_l_loop_100_sw,
                                                     p_l_loop_100_e,
                                                     p_l_loop_100_w,
                                                     link_100_out_n,
                                                     link_100_out_ne,
                                                     link_100_out_nw,
                                                     link_100_out_s,
                                                     link_100_out_se,
                                                     link_100_out_sw,
                                                     link_100_out_e,
                                                     link_100_out_w,
                                                     link_100_controller_complete,
                                                     link_100_controller_final_label
                                                   );

  link_controller_101   : link_controller port map ( controller_clk,
                                                     link_101_address,
                                                     link_101_controller_pixel,
                                                     p_l_loop_101_n,
                                                     physical_link_4_101,
                                                     p_l_loop_101_nw,
                                                     p_l_loop_101_s,
                                                     p_l_loop_101_se,
                                                     p_l_loop_101_sw,
                                                     p_l_loop_101_e,
                                                     p_l_loop_101_w,
                                                     link_101_out_n,
                                                     link_101_out_ne,
                                                     link_101_out_nw,
                                                     link_101_out_s,
                                                     link_101_out_se,
                                                     link_101_out_sw,
                                                     link_101_out_e,
                                                     link_101_out_w,
                                                     link_101_controller_complete,
                                                     link_101_controller_final_label
                                                   );


  --------------------------------------------------------------------------------------------------------
  --
  -- physical links linkage
  --
  --
  --
  --------------------------------------------------------------------------------------------------------

  link_1_2             : link_physical port map (link_1_out_e    , link_2_out_w    , physical_link_1_2 );
  link_1_3             : link_physical port map (link_1_out_s    , link_3_out_n    , physical_link_1_3 );
  link_1_4             : link_physical port map (link_1_out_se   , link_4_out_nw   , physical_link_1_4 );

  link_2_3             : link_physical port map (link_2_out_sw   , link_3_out_ne   , physical_link_2_3 );
  link_2_4             : link_physical port map (link_2_out_s    , link_4_out_n    , physical_link_2_4 );

  link_3_4             : link_physical port map (link_3_out_e    , link_4_out_w    , physical_link_3_4 );


  --------------------------------------------------------------------------------------------------------
  --
  -- active controllers links to boundary links
  --
  --
  --
  --------------------------------------------------------------------------------------------------------

  link_1_90           : link_physical port map (link_1_out_nw   , link_90_out_se  , physical_link_1_90 );
  link_1_91           : link_physical port map (link_1_out_n    , link_91_out_s   , physical_link_1_91 );
  link_1_92           : link_physical port map (link_1_out_ne   , link_92_out_sw  , physical_link_1_92 );
  link_1_94           : link_physical port map (link_1_out_w    , link_94_out_e   , physical_link_1_94 );
  link_1_96           : link_physical port map (link_1_out_sw   , link_96_out_ne  , physical_link_1_96 );

  link_2_91           : link_physical port map (link_2_out_nw   , link_91_out_se  , physical_link_2_91 );
  link_2_92           : link_physical port map (link_2_out_n    , link_92_out_s   , physical_link_2_92 );
  link_2_93           : link_physical port map (link_2_out_ne   , link_93_out_sw  , physical_link_2_93 );
  link_2_95           : link_physical port map (link_2_out_e    , link_95_out_w   , physical_link_2_95 );
  link_2_97           : link_physical port map (link_2_out_se   , link_97_out_nw  , physical_link_2_97 );

  link_3_94           : link_physical port map (link_3_out_nw   , link_94_out_se  , physical_link_3_94 );
  link_3_96           : link_physical port map (link_3_out_w    , link_96_out_e   , physical_link_3_96 );
  link_3_98           : link_physical port map (link_3_out_sw   , link_98_out_ne  , physical_link_3_98 );
  link_3_99           : link_physical port map (link_3_out_s    , link_99_out_n   , physical_link_3_99 );
  link_3_100          : link_physical port map (link_3_out_se   , link_100_out_nw , physical_link_3_100);

  link_4_99           : link_physical port map (link_4_out_sw   , link_99_out_ne  , physical_link_4_99 );
  link_4_100          : link_physical port map (link_4_out_s    , link_100_out_n  , physical_link_4_100);
  link_4_101          : link_physical port map (link_4_out_se   , link_101_out_nw , physical_link_4_101);
  link_4_97           : link_physical port map (link_4_out_e    , link_97_out_w   , physical_link_4_97 );
  link_4_95           : link_physical port map (link_4_out_ne   , link_95_out_sw  , physical_link_4_95 );

  --------------------------------------------------------------------------------------------------------
  --
  -- boundary loop back links linkage
  --
  --
  --
  --------------------------------------------------------------------------------------------------------

  link_l_90_n         : link_physical port map (link_90_out_n   , link_90_out_n   , p_l_loop_90_n      );
  link_l_90_ne        : link_physical port map (link_90_out_ne  , link_90_out_ne  , p_l_loop_90_ne     );
  link_l_90_nw        : link_physical port map (link_90_out_nw  , link_90_out_nw  , p_l_loop_90_nw     );
  link_l_90_s         : link_physical port map (link_90_out_s   , link_90_out_s   , p_l_loop_90_s      );
  link_l_90_sw        : link_physical port map (link_90_out_sw  , link_90_out_sw  , p_l_loop_90_sw     );
  link_l_90_e         : link_physical port map (link_90_out_e   , link_90_out_e   , p_l_loop_90_e      );
  link_l_90_w         : link_physical port map (link_90_out_w   , link_90_out_w   , p_l_loop_90_w      );

  link_l_91_n         : link_physical port map (link_91_out_n   , link_91_out_n   , p_l_loop_91_n      );
  link_l_91_ne        : link_physical port map (link_91_out_ne  , link_91_out_ne  , p_l_loop_91_ne     );
  link_l_91_nw        : link_physical port map (link_91_out_nw  , link_91_out_nw  , p_l_loop_91_nw     );
  link_l_91_sw        : link_physical port map (link_91_out_sw  , link_91_out_sw  , p_l_loop_91_sw     );
  link_l_91_e         : link_physical port map (link_91_out_e   , link_91_out_e   , p_l_loop_91_e      );
  link_l_91_w         : link_physical port map (link_91_out_w   , link_91_out_w   , p_l_loop_91_w      );

  link_l_92_n         : link_physical port map (link_92_out_n   , link_92_out_n   , p_l_loop_92_n      );
  link_l_92_ne        : link_physical port map (link_92_out_ne  , link_92_out_ne  , p_l_loop_92_ne     );
  link_l_92_nw        : link_physical port map (link_92_out_nw  , link_92_out_nw  , p_l_loop_92_nw     );
  link_l_92_se        : link_physical port map (link_92_out_se  , link_92_out_se  , p_l_loop_92_se     );
  link_l_92_e         : link_physical port map (link_92_out_e   , link_92_out_e   , p_l_loop_92_e      );
  link_l_92_w         : link_physical port map (link_92_out_w   , link_92_out_w   , p_l_loop_92_w      );

  link_l_93_n         : link_physical port map (link_93_out_n   , link_93_out_n   , p_l_loop_93_n      );
  link_l_93_ne        : link_physical port map (link_93_out_ne  , link_93_out_ne  , p_l_loop_93_ne     );
  link_l_93_nw        : link_physical port map (link_93_out_nw  , link_93_out_nw  , p_l_loop_93_nw     );
  link_l_93_s         : link_physical port map (link_93_out_s   , link_93_out_s   , p_l_loop_93_s      );
  link_l_93_se        : link_physical port map (link_93_out_se  , link_93_out_se  , p_l_loop_93_se     );
  link_l_93_e         : link_physical port map (link_93_out_e   , link_93_out_e   , p_l_loop_93_e      );
  link_l_93_w         : link_physical port map (link_93_out_w   , link_93_out_w   , p_l_loop_93_w      );

  link_l_94_n         : link_physical port map (link_94_out_n   , link_94_out_n   , p_l_loop_94_n      );
  link_l_94_ne        : link_physical port map (link_94_out_ne  , link_94_out_ne  , p_l_loop_94_ne     );
  link_l_94_nw        : link_physical port map (link_94_out_nw  , link_94_out_nw  , p_l_loop_94_nw     );
  link_l_94_s         : link_physical port map (link_94_out_s   , link_94_out_s   , p_l_loop_94_s      );
  link_l_94_sw        : link_physical port map (link_94_out_sw  , link_94_out_sw  , p_l_loop_94_sw     );
  link_l_94_w         : link_physical port map (link_94_out_w   , link_94_out_w   , p_l_loop_94_w      );

  link_l_95_n         : link_physical port map (link_95_out_n   , link_95_out_n   , p_l_loop_95_n      );
  link_l_95_ne        : link_physical port map (link_95_out_ne  , link_95_out_ne  , p_l_loop_95_ne     );
  link_l_95_nw        : link_physical port map (link_95_out_nw  , link_95_out_nw  , p_l_loop_95_nw     );
  link_l_95_s         : link_physical port map (link_95_out_s   , link_95_out_s   , p_l_loop_95_s      );
  link_l_95_se        : link_physical port map (link_95_out_se  , link_95_out_se  , p_l_loop_95_se     );
  link_l_95_sw        : link_physical port map (link_95_out_sw  , link_95_out_sw  , p_l_loop_95_sw     );
  link_l_95_e         : link_physical port map (link_95_out_e   , link_95_out_e   , p_l_loop_95_e      );

  link_l_96_n         : link_physical port map (link_96_out_n   , link_96_out_n   , p_l_loop_96_n      );
  link_l_96_nw        : link_physical port map (link_96_out_nw  , link_96_out_nw  , p_l_loop_96_nw     );
  link_l_96_s         : link_physical port map (link_96_out_s   , link_96_out_s   , p_l_loop_96_s      );
  link_l_96_se        : link_physical port map (link_96_out_se  , link_96_out_se  , p_l_loop_96_se     );
  link_l_96_sw        : link_physical port map (link_96_out_sw  , link_96_out_sw  , p_l_loop_96_sw     );
  link_l_96_w         : link_physical port map (link_96_out_w   , link_96_out_w   , p_l_loop_96_w      );

  link_l_97_n         : link_physical port map (link_97_out_n   , link_97_out_n   , p_l_loop_97_n      );
  link_l_97_ne        : link_physical port map (link_97_out_ne  , link_97_out_ne  , p_l_loop_97_ne     );
  link_l_97_s         : link_physical port map (link_97_out_s   , link_97_out_s   , p_l_loop_97_s      );
  link_l_97_se        : link_physical port map (link_97_out_se  , link_97_out_se  , p_l_loop_97_se     );
  link_l_97_sw        : link_physical port map (link_97_out_sw  , link_97_out_sw  , p_l_loop_97_sw     );
  link_l_97_e         : link_physical port map (link_97_out_e   , link_97_out_e   , p_l_loop_97_e      );

  link_l_98_n         : link_physical port map (link_98_out_n   , link_98_out_n   , p_l_loop_98_n      );
  link_l_98_ne        : link_physical port map (link_98_out_ne  , link_98_out_ne  , p_l_loop_98_ne     );
  link_l_98_nw        : link_physical port map (link_98_out_nw  , link_98_out_nw  , p_l_loop_98_nw     );
  link_l_98_s         : link_physical port map (link_98_out_s   , link_98_out_s   , p_l_loop_98_s      );
  link_l_98_se        : link_physical port map (link_98_out_se  , link_98_out_se  , p_l_loop_98_se     );
  link_l_98_sw        : link_physical port map (link_98_out_sw  , link_98_out_sw  , p_l_loop_98_sw     );
  link_l_98_e         : link_physical port map (link_98_out_e   , link_98_out_e   , p_l_loop_98_e      );
  link_l_98_w         : link_physical port map (link_98_out_w   , link_98_out_w   , p_l_loop_98_w      );

  link_l_99_ne        : link_physical port map (link_99_out_ne  , link_99_out_ne  , p_l_loop_99_ne     );
  link_l_99_nw        : link_physical port map (link_99_out_nw  , link_99_out_nw  , p_l_loop_99_nw     );
  link_l_99_s         : link_physical port map (link_99_out_s   , link_99_out_s   , p_l_loop_99_s      );
  link_l_99_se        : link_physical port map (link_99_out_se  , link_99_out_se  , p_l_loop_99_se     );
  link_l_99_sw        : link_physical port map (link_99_out_sw  , link_99_out_sw  , p_l_loop_99_sw     );
  link_l_99_e         : link_physical port map (link_99_out_e   , link_99_out_e   , p_l_loop_99_e      );
  link_l_99_w         : link_physical port map (link_99_out_w   , link_99_out_w   , p_l_loop_99_w      );

  link_l_100_ne       : link_physical port map (link_100_out_ne , link_100_out_ne , p_l_loop_100_ne    );
  link_l_100_nw       : link_physical port map (link_100_out_nw , link_100_out_nw , p_l_loop_100_nw    );
  link_l_100_s        : link_physical port map (link_100_out_s  , link_100_out_s  , p_l_loop_100_s     );
  link_l_100_se       : link_physical port map (link_100_out_se , link_100_out_se , p_l_loop_100_se    );
  link_l_100_sw       : link_physical port map (link_100_out_sw , link_100_out_sw , p_l_loop_100_sw    );
  link_l_100_e        : link_physical port map (link_100_out_e  , link_100_out_e  , p_l_loop_100_e     );
  link_l_100_w        : link_physical port map (link_100_out_w  , link_100_out_w  , p_l_loop_100_w     );

  link_l_101_n        : link_physical port map (link_101_out_n  , link_101_out_n  , p_l_loop_101_n     );
  link_l_101_nw       : link_physical port map (link_101_out_nw , link_101_out_nw , p_l_loop_101_nw    );
  link_l_101_s        : link_physical port map (link_101_out_s  , link_101_out_s  , p_l_loop_101_s     );
  link_l_101_se       : link_physical port map (link_101_out_se , link_101_out_se , p_l_loop_101_se    );
  link_l_101_sw       : link_physical port map (link_101_out_sw , link_101_out_sw , p_l_loop_101_sw    );
  link_l_101_e        : link_physical port map (link_101_out_e  , link_101_out_e  , p_l_loop_101_e     );
  link_l_101_w        : link_physical port map (link_101_out_w  , link_101_out_w  , p_l_loop_101_w     );


  process

    variable out_loop : integer := 0;

    variable controller_label : integer := 1;
    variable border_label : integer := 90;

    procedure clock_link is
    begin
      controller_clk <= '1';
      wait for 1 ns;
      controller_clk <= '0';
      wait for 1 ns;
    end clock_link;

    procedure print_any_label ( print_label : std_logic_vector ) is
    begin

      report ("Printing Final Label: " & std_logic'image(print_label(31))
                                       & std_logic'image(print_label(30))
                                       & std_logic'image(print_label(29))
                                       & std_logic'image(print_label(28))
                                       & std_logic'image(print_label(27))
                                       & std_logic'image(print_label(26))
                                       & std_logic'image(print_label(25))
                                       & std_logic'image(print_label(24))
                                       & std_logic'image(print_label(23))
                                       & std_logic'image(print_label(22))
                                       & std_logic'image(print_label(21))
                                       & std_logic'image(print_label(20))
                                       & std_logic'image(print_label(19))
                                       & std_logic'image(print_label(18))
                                       & std_logic'image(print_label(17))
                                       & std_logic'image(print_label(16))
                                       & std_logic'image(print_label(15))
                                       & std_logic'image(print_label(14))
                                       & std_logic'image(print_label(13))
                                       & std_logic'image(print_label(12))
                                       & std_logic'image(print_label(11))
                                       & std_logic'image(print_label(10))
                                       & std_logic'image(print_label(9))
                                       & std_logic'image(print_label(8))
                                       & std_logic'image(print_label(7))
                                       & std_logic'image(print_label(6))
                                       & std_logic'image(print_label(5))
                                       & std_logic'image(print_label(4))
                                       & std_logic'image(print_label(3))
                                       & std_logic'image(print_label(2))
                                       & std_logic'image(print_label(1))
                                       & std_logic'image(print_label(0)));

    end procedure print_any_label;

    procedure print_all_final_labels is
    begin

      print_any_label(link_1_controller_final_label);
      print_any_label(link_2_controller_final_label);
      print_any_label(link_3_controller_final_label);
      print_any_label(link_4_controller_final_label);

    end procedure print_all_final_labels;

    impure function are_all_controllers_complete return std_logic is
      variable result : std_logic := '1';
    begin

      result := result and link_1_controller_complete;
      result := result and link_2_controller_complete;
      result := result and link_3_controller_complete;
      result := result and link_4_controller_complete;

      return result;

    end function are_all_controllers_complete;

  begin

    --------------------------------------------------------------------------------------------------------
    --
    -- set controller pixel values
    --
    --------------------------------------------------------------------------------------------------------
    link_1_controller_pixel <= '1';
    link_2_controller_pixel <= '1';
    link_3_controller_pixel <= '1';
    link_4_controller_pixel <= '1';

    link_90_controller_pixel <= '0';
    link_91_controller_pixel <= '0';
    link_92_controller_pixel <= '0';
    link_93_controller_pixel <= '0';
    link_94_controller_pixel <= '0';
    link_95_controller_pixel <= '0';
    link_96_controller_pixel <= '0';
    link_97_controller_pixel <= '0';
    link_98_controller_pixel <= '0';
    link_99_controller_pixel <= '0';
    link_100_controller_pixel <= '0';
    link_101_controller_pixel <= '0';
    wait for 1000 ns;

    --------------------------------------------------------------------------------------------------------
    --
    -- set controller addresses
    --
    --------------------------------------------------------------------------------------------------------
    link_1_address   <= "00000000000000000000000000000001";
    link_2_address   <= "00000000000000000000000000000010";
    link_3_address   <= "00000000000000000000000000000101";
    link_4_address   <= "00000000000000000000000000000100";

    link_90_address  <= "10000000000000000000000000000000";
    link_91_address  <= "10000000000000000000000000000000";
    link_92_address  <= "10000000000000000000000000000000";
    link_93_address  <= "10000000000000000000000000000000";
    link_94_address  <= "10000000000000000000000000000000";
    link_95_address  <= "10000000000000000000000000000000";
    link_96_address  <= "10000000000000000000000000000000";
    link_97_address  <= "10000000000000000000000000000000";
    link_98_address  <= "10000000000000000000000000000000";
    link_99_address  <= "10000000000000000000000000000000";
    link_100_address <= "10000000000000000000000000000000";
    link_101_address <= "10000000000000000000000000000000";

    wait for 1000 ns;

    --------------------------------------------------------------------------------------------------------
    --
    -- initialize all links with 3 clock cycles
    --
    --------------------------------------------------------------------------------------------------------
    clock_link;
    clock_link;
    clock_link;

    while are_all_controllers_complete = '0' loop

      out_loop := out_loop + 1;
      report ("Clocking Com: " & integer'image(out_loop));

      clock_link;
      clock_link;

      -- link reset is read on this cycle

      clock_link;
      clock_link;
      clock_link;
      
      -- link data set on this clock cycle

      clock_link;
      clock_link;
      clock_link;

      clock_link;
      clock_link;

      clock_link;
      clock_link;
      clock_link;


    end loop;

    --------------------------------------------------------------------------------------------------------
    --
    -- print out final labels
    --
    --------------------------------------------------------------------------------------------------------
    report ("Number Of Communication Cycles to Converge: " & integer'image( out_loop ));
    print_all_final_labels;

    wait;

  end process;

end tb;
